Reducing the number of LUTs for Mealy FSMs with state transformation - Barkalov, Alexander; Titarenko, Larysa; Mielcarek, Kamil (Zielona Góra: Uniwersytet Zielonogórski)
In many digital systems, various sequential blocks are used. This paper is devoted to the case where the model of a Mealy finite state machine (FSM) represents the behaviour of a sequential block. The chip area occupied by an FSMcircuit is one of the most important characteristics used in logic synthesis.
Keywords: mealy FSM; FPGA; LUT; synthesis; extended state codes; combined state codes