TY - GEN A1 - Szabó, Tamás A1 - Horváth, Gábor A2 - Korbicz, Józef - red. A2 - Patton, Ronald J. - red. PB - Zielona Góra: Uniwersytet Zielonogórski N2 - This paper deals with the family of CMAC neural networks. The most important properties of this family are the extremely fast learning capability and a special architecture that makes effective digital hardware implementation possible. The paper gives an overview of the classical binary CMAC, shows the limitations of its modelling capability, gives a critical survey of its different extensions and suggests two further modifications. N2 - The aim of these modifications is to improve the modelling capability while maintaining the possibility of an effective realization. The basic element of the first suggested hardware structure is a new matrix-vector multiplier which is based on a canonical signed digit (CSD) number representation and a distributed arithmetic. N2 - In the other version, a hierarchical network structure and a special sequential training method are proposed which can constitute a trade-off between the approximation error and generalization. The proposed versions (among them a dynamic extension of the originally static CMAC) are suitable for embedded applications where the low cost and relatively high speed operation are the most important requirements. L1 - http://zbc.uz.zgora.pl/repozytorium/Content/58186/AMCS_1999_9_3_4.pdf L2 - http://zbc.uz.zgora.pl/repozytorium/Content/58186 KW - CMAC KW - neural networks KW - B-splines KW - hardware implementation T1 - CMAC and its extensions for efficient system modelling UR - http://zbc.uz.zgora.pl/repozytorium/dlibra/docmetadata?id=58186 ER -