Creator:
Syarnsuddin, E.Y. ; Hicks, Peter J.
Contributor:
Title:
Microelectronics sensor arrays with integral processing capability
Subtitle:
Proceedings of the ACEP Workshop - Borowice (1992)
Group publication title:
Subject and Keywords:
sterowanie ; sterowanie-teoria ; sztuczna inteligencja ; matematyka stosowana ; informatyka
Abstract:
A "smart" image sensor is described which is capable of performing low-level preprocessing of image data in parallel with the sensing operation. The chip consists of an array of 32 x 32 image sensing and storage cells and associated output circuits. The array is able to capture an image and simultaneously store the current and previous frames on separate capacitors located within each pixel site. Having the storage capacitors integrated into the sensing cells overcomes problems due to parasitic capacitance on the output lines which in turn improves the signal-to-noise ratio. ; The photocharge generated in the photodiode sensors is sensed nondestructively, using a buffer amplifier prior to being sampled onto the local capacitor. The charge on each capacitor is sensed in turn in the same manner prior to being dumped to the output line. The output circuitry consists of a parallel array of differential amplifiers and comparators. The amplifiers perform frame-differencing between the current and previous frames while the comparators are used for global thresholding. ; The frame-differencing and thresholding modes can be enabled and disabled independently. The chip has been fabricated in a 2.4 ? double-poly CMOS process and is intended for use as a front-end in motion detection applications. At present its operation is limited to the calculation of differences between two successive frames. ; Further development would be needed in order for the chip to be used as a motion detector, in particular the tasks of edge-detection and region classification would need to be implemented. Since the objective was to achieve motion detection in real-time it is intended that these operations should be performed in hardware. It is for this reason that the outputs from the 2-dimensional imaging array are presented in parallel.
Publisher:
Zielona Góra: Uniwersytet Zielonogórski
Date:
Resource Type:
Pages:
Source:
AMCS, volume 3, number 1 (1993) ; click here to follow the link