Autor:

Barkalov, Alexander ; Titarenko, Larysa ; Chmielewski, Sławomir

Współtwórca:

Korbicz, Józef (1951- ) - red.

Tytuł:

Reduction in the number of PAL macrocells in the circuit of a Moore FSM

Tytuł publikacji grupowej:

AMCS, volume 17 (2007)

Temat i słowa kluczowe:

Moore finite-state machine ; complex programmable logic devices ; design ; logic circuit ; pseudoequivalent states

Abstract:

Optimization methods of logic circuits for Moore finite-state machines are proposed. These methods are based on the existence of pseudoequivalent states of a Moore finite-state machine, a wide fan-in of PAL macrocells and free resources of embedded memory blocks. The methods are oriented to hypothetical VLSI microcircuits based on the CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm to choose the best model of a finite-state machine for given conditions is proposed. Examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated.

Wydawca:

Zielona Góra: Uniwersytet Zielonogórski

Data wydania:

2007

Typ zasobu:

artykuł

DOI:

10.2478/v10006-007-0046-8

Strony:

565-575

Źródło:

AMCS, volume 17, number 4 (2007) ; kliknij tutaj, żeby przejść

Jezyk:

eng

Licencja CC BY 4.0:

kliknij tutaj, żeby przejść

Prawa do dysponowania publikacją:

Biblioteka Uniwersytetu Zielonogórskiego