Creator:

Barkalov, Alexander ; Titarenko, Larysa ; Mielcarek, Kamil

Contributor:

Korbicz, Józef (1951- ) - red. ; Uciński, Dariusz - red.

Title:

Hardware reduction for LUT-based Mealy FSMs

Group publication title:

AMCS, volume 28 (2018)

Subject and Keywords:

mealy FSM ; synthesis ; FPGA ; LUT ; partitions ; encoding collections of output variables

Abstract:

A method is proposed targeting a decrease in the number of LUTs in circuits of FPGA-based Mealy FSMs. The method improves hardware consumption for Mealy FSMs with the encoding of collections of output variables. The approach is based on constructing a partition for the set of internal states. Each state has two codes. It diminishes the number of arguments in input memory functions. An example of synthesis is given, along with results of investigations. The method targets rather complex FSMs, having more than 15 states.

Publisher:

Zielona Góra: Uniwersytet Zielonogórski

Date:

2018

Resource Type:

artykuł

DOI:

10.2478/amcs-2018-0046

Pages:

595-607

Source:

AMCS, volume 28, number 3 (2018) ; click here to follow the link

Language:

eng

License CC BY 4.0:

click here to follow the link

Rights:

Biblioteka Uniwersytetu Zielonogórskiego