Repozytorium Uniwersytetu Zielonogórskiego udostępnia 9 272 obiektów cyfrowych
Obiekt
Tytuł: Reducing the number of LUTs for Mealy FSMs with state transformation
Współtwórca:
Korbicz, Józef (1951- ) - red. ; Uciński, Dariusz - red.
Tytuł publikacji grupowej:
Abstract:
In many digital systems, various sequential blocks are used. This paper is devoted to the case where the model of a Mealy finite state machine (FSM) represents the behaviour of a sequential block. The chip area occupied by an FSMcircuit is one of the most important characteristics used in logic synthesis. ; In this paper, a method is proposed which aims at reducing LUT counts for FPGA-based Mealy FSMs with transformation of state codes into FSM outputs. This is done using the combined state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed method leads to LUT-based Mealy FSM circuits having exactly three levels of logic blocks. Under certain conditions, each function for any logic level is represented by a circuit including a single LUT. ; The proposed approach is illustrated with an example of synthesis. The results of experiments conducted using standard benchmarks show that the proposed method produces LUT-based FSM circuits with significantly smaller LUT counts than is the case for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and transformation of binary codes into extended state codes). ; The LUT count is decreased by an average of 17.96 to 91.8%. Moreover, if some conditions are met, the decrease in the LUT count is accompanied with a slight improvement in the operating frequency compared with circuits based on extended state codes. The advantages of the proposed method multiply with increasing the numbers of FSM inputs and states.
Wydawca:
Zielona Góra: Uniwersytet Zielonogórski
Identyfikator zasobu:
DOI:
Strony:
Źródło:
AMCS, volume 34, number 1 (2024) ; kliknij tutaj, żeby przejść
Jezyk:
Licencja CC BY 4.0:
Prawa do dysponowania publikacją:
Biblioteka Uniwersytetu Zielonogórskiego
Kolekcje, do których przypisany jest obiekt:
- Repozytorium > Jednostki organizacyjne > Wydział Informatyki, Elektrotechniki i Automatyki
- Repozytorium > Typy utworów > Artykuły
- Repozytorium > Czasopisma naukowe i serie wydawnicze UZ > International Journal of Applied Mathematics and Computer Science (AMCS) > International Journal of Applied Mathematics and Computer Science (AMCS) (2024)
Data ostatniej modyfikacji:
29 lip 2025
Data dodania obiektu:
29 lip 2025
Liczba wyświetleń treści obiektu:
13
Wszystkie dostępne wersje tego obiektu:
https://zbc.uz.zgora.pl/repozytorium/publication/101662
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International Journal of Applied Mathematics and Computer Science (AMCS), volume 34, number 1 (2024)
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International Journal of Applied Mathematics and Computer Science (AMCS), volume 34, number 2 (2024)
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International Journal of Applied Mathematics and Computer Science (AMCS), volume 34, number 3 (2024)
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International Journal of Applied Mathematics and Computer Science (AMCS), volume 34, number 4 (2024)
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| Nazwa wydania | Data |
|---|---|
| Reducing the number of LUTs for Mealy FSMs with state transformation | 29 lip 2025 |
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