Szukana fraza: [Abstract = "Logic verification is based on the transformation of different levels of circuit description. to a common, canonical form. Binary Decision Diagrams \(BDD\) are used for this purpose because of their capability to produce simple models for the results of arithmetic addition. Logic verification is a numerically complex task, which limits its usefulness. Parallel processing on a multi\-transputer system can make it more attractive. It is proposed to introduce the parallel processing at the level of constructing the decision diagrams \(BDD Engine\)."]
