Gałkowski, Krzysztof - ed. ; Rogers, Eric - ed. ; Willems, Jan
This work presents the first self-checking Booth-3 multiplier and a new self-checking Booth-2 multiplier using parity prediction. We propose a method which combines error-detection of Booth-3 (or Booth-2) decoder cells and parity prediction. Additionally, code disjointness is ensured by reusing logic for partial product generation. Parity prediction is applied to a carry-save-adder with the standard sign-bit extension. ; In this adder almost all cells have odd fanouts and faults are detected by the parity. Only one adder cell has an even fanout in the case of Booth-3 multiplication. Especially, for even-number Booth-2 multipliers parity prediction becomes efficient. Since that prediction slightly differs from previous work which describes CSA-folded adders, formulas to predict the parity are developed here. The proposed multipliers are compared experimentally with existing solutions. Only 102% of the area of Booth-2 without error detection is needed for the self-checking Booth-3 multiplier.
Zielona Góra: Uniwersytet Zielonogórski
AMCS, volume 18, number 3 (2008) ; kliknij tutaj, żeby przejść
Biblioteka Uniwersytetu Zielonogórskiego
2024-04-08
2024-04-05
50
https://zbc.uz.zgora.pl/publication/88482
Nazwa wydania | Data |
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New self-checking Booth multipliers | 2024-04-08 |