Korbicz, Józef (1951- ) - red. ; Uciński, Dariusz - red.
In this paper, novel pipelined architectures for the implementation of the frequency domain linear equalizer are presented. The Frequency Domain (FD) LMS algorithm is utilized for the adaptation of equalizer coefficients. The pipelining of the FD LMS linear equalizer is achieved by introducing an amount of time delay into the original adaptive scheme, and following proper delay retiming. ; Simulation results are presented that illustrate the performance of the effect of the time delay introduced into the adaptation algorithm. The proposed architectures for efficient pipelining of the FD LMS linear equalization algorithm are suitable for implementation on special purpose hardware by means of the ASIC, ASIP or FPGA VLSI processors.
Zielona Góra: Uniwersytet Zielonogórski
AMCS, volume 16, number 4 (2006) ; kliknij tutaj, żeby przejść
Biblioteka Uniwersytetu Zielonogórskiego
2024-11-05
2020-08-26
77
https://zbc.uz.zgora.pl/publication/64118
Nazwa wydania | Data |
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Pipelined architectures for the frequency domain linear equalizer | 2024-11-05 |
Glentis, George-Othon Korbicz, Józef (1951- ) - red. Uciński, Dariusz - red.