Proceedings of the ACEP Workshop - Borowice (1992)
Logic verification is based on the comparison of a circuit behavioural specification with its structural realisation. It plays an important part in VLSI design. The circuit descriptions are expressed in a hardware description language. A modified language may simplify the verification process, e.g. the NODEN HDL. ; Logic verification is based on the transformation of different levels of circuit description. to a common, canonical form. Binary Decision Diagrams (BDD) are used for this purpose because of their capability to produce simple models for the results of arithmetic addition. Logic verification is a numerically complex task, which limits its usefulness. Parallel processing on a multi-transputer system can make it more attractive. It is proposed to introduce the parallel processing at the level of constructing the decision diagrams (BDD Engine).
Zielona Góra: Uniwersytet Zielonogórski
AMCS, volume 3, number 1 (1993) ; kliknij tutaj, żeby przejść
Biblioteka Uniwersytetu Zielonogórskiego
2021-09-01
2020-07-06
70
https://zbc.uz.zgora.pl/repozytorium/publication/63816
Nazwa wydania | Data |
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A BDD engine for logic verification | 2021-09-01 |
Beliczyński, Bartłomiej - red.
Krasoń, Ewa Kaczorek, Tadeusz - ed.
Trzaska, Zdzisław W. Kaczorek, Tadeusz - ed.
Xu, Li Saito, Osami Abe, Kenichi Kaczorek, Tadeusz - ed.
Young, K. David Yu, Xinghuo - red.
Xu, Jian-Xin Song, Yanbin Yu, Xinghuo - red.