Digital Library of Zielona Góra contains 9 272 digital objects
Object
Title: A BDD engine for logic verification
Contributor:
Subtitle:
Proceedings of the ACEP Workshop - Borowice (1992)
Group publication title:
Abstract:
Logic verification is based on the comparison of a circuit behavioural specification with its structural realisation. It plays an important part in VLSI design. The circuit descriptions are expressed in a hardware description language. A modified language may simplify the verification process, e.g. the NODEN HDL. ; Logic verification is based on the transformation of different levels of circuit description. to a common, canonical form. Binary Decision Diagrams (BDD) are used for this purpose because of their capability to produce simple models for the results of arithmetic addition. Logic verification is a numerically complex task, which limits its usefulness. Parallel processing on a multi-transputer system can make it more attractive. It is proposed to introduce the parallel processing at the level of constructing the decision diagrams (BDD Engine).
Publisher:
Zielona Góra: Uniwersytet Zielonogórski
Resource Identifier:
Pages:
Source:
AMCS, volume 3, number 1 (1993) ; click here to follow the link
Language:
License CC BY 4.0:
Rights:
Biblioteka Uniwersytetu Zielonogórskiego
Object collections:
- Repository > Faculties > Faculty of Computer, Electrical and Control Engineering
- Repository > Types of work > Articles
- Repository > Scientific journals and UZ publishing series > International Journal of Applied Mathematics and Computer Science (AMCS) > International Journal of Applied Mathematics and Computer Science (AMCS) (1993)
Last modified:
Jul 14, 2025
In our library since:
Jul 6, 2020
Number of object content hits:
138
All available object's versions:
https://zbc.uz.zgora.pl/repozytorium/publication/63816
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| Edition name | Date |
|---|---|
| A BDD engine for logic verification | Jul 14, 2025 |
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